Display panel driver and display panel driving method

A display panel driver includes: a clock generator for generating a clock signal; a horizontal reference generating circuit having a first frequency divider for dividing the frequency of the clock signal; a vertical reference generating circuit having a second frequency divider for dividing the frequency of the output from the first frequency divider; a switch circuit having one input terminal to which an external vertical synchronizing signal is supplied and having another input terminal to which the output signal from the second frequency divider is supplied and which selectively output one of said input terminals; and a CPU that alters the oscillation frequency of the clock generator or the frequency division ratio at the first frequency divider when a switching between the input terminals of the switch circuit is performed.