Packet processors having comparators therein that determine non-strict inequalities between applied operands
o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1,...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Wen, Tingjun Carr, David Walter Kwasniewski, Tadeusz |
description | o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: "n" is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C. |
format | Patent |
fullrecord | <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07825777</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07825777</sourcerecordid><originalsourceid>FETCH-uspatents_grants_078257773</originalsourceid><addsrcrecordid>eNqNyjEKAjEQheFtLES9w1xgQRSJvSiWFvYyZp9rMDuJmVm9vhE8gNXHe_zTJp7YP2CUS_JQTUXpzq8gPfk0ZC5s38vuKAhSZaMOhjIEAUmSVq0Eb1Tnc-QYLEDpCnsDQpxzDOgoZRSWTufN5MZRsfg5a-iwP--O7aiZDWJ66WtYWbrtauOcW_-RfACN-UQq</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Packet processors having comparators therein that determine non-strict inequalities between applied operands</title><source>USPTO Issued Patents</source><creator>Wen, Tingjun ; Carr, David Walter ; Kwasniewski, Tadeusz</creator><creatorcontrib>Wen, Tingjun ; Carr, David Walter ; Kwasniewski, Tadeusz ; Integrated Device Technology, Inc</creatorcontrib><description>o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: "n" is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7825777$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7825777$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Wen, Tingjun</creatorcontrib><creatorcontrib>Carr, David Walter</creatorcontrib><creatorcontrib>Kwasniewski, Tadeusz</creatorcontrib><creatorcontrib>Integrated Device Technology, Inc</creatorcontrib><title>Packet processors having comparators therein that determine non-strict inequalities between applied operands</title><description>o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: "n" is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNyjEKAjEQheFtLES9w1xgQRSJvSiWFvYyZp9rMDuJmVm9vhE8gNXHe_zTJp7YP2CUS_JQTUXpzq8gPfk0ZC5s38vuKAhSZaMOhjIEAUmSVq0Eb1Tnc-QYLEDpCnsDQpxzDOgoZRSWTufN5MZRsfg5a-iwP--O7aiZDWJ66WtYWbrtauOcW_-RfACN-UQq</recordid><startdate>20101102</startdate><enddate>20101102</enddate><creator>Wen, Tingjun</creator><creator>Carr, David Walter</creator><creator>Kwasniewski, Tadeusz</creator><scope>EFH</scope></search><sort><creationdate>20101102</creationdate><title>Packet processors having comparators therein that determine non-strict inequalities between applied operands</title><author>Wen, Tingjun ; Carr, David Walter ; Kwasniewski, Tadeusz</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_078257773</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Wen, Tingjun</creatorcontrib><creatorcontrib>Carr, David Walter</creatorcontrib><creatorcontrib>Kwasniewski, Tadeusz</creatorcontrib><creatorcontrib>Integrated Device Technology, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Wen, Tingjun</au><au>Carr, David Walter</au><au>Kwasniewski, Tadeusz</au><aucorp>Integrated Device Technology, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Packet processors having comparators therein that determine non-strict inequalities between applied operands</title><date>2010-11-02</date><risdate>2010</risdate><abstract>o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: "n" is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_uspatents_grants_07825777 |
source | USPTO Issued Patents |
title | Packet processors having comparators therein that determine non-strict inequalities between applied operands |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T00%3A01%3A08IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Wen,%20Tingjun&rft.aucorp=Integrated%20Device%20Technology,%20Inc&rft.date=2010-11-02&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07825777%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |