Packet processors having comparators therein that determine non-strict inequalities between applied operands

o i oAn integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal C(or its complement), where: "n" is a positive integer greater than one and Cis a control input signal that specifies an interpretation to be given to the control output signal C.