Combined response cancellation for load command
A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power...
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| Hauptverfasser: | , , |
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption. |
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