Leakage power optimization considering gate input activity and timing slack

Broadly speaking, the embodiments of the present invention fill the need for a method of designing semiconductor device chips with reduced power consumption. The embodiments describe methods that are activity-based and are used for power optimization. The embodiments provide methods of selecting instances of a block of a chip to be replaced by either gate-length bias (GBIAS) cells or high-threshold-voltage (HVT) cells with minimal impact (little or no impact) on the overall performance of the chip. Only instances not on the critical path(s) are selected. Instances with low activities and high slack thresholds are chosen to be replaced by either GBIAS cells or HVT cells. By replacing the instances with low activities and high slack threshold, the performance impact on the block and chip is minimized. The replacement results in net power reduction, which is critical to advanced device technologies.