Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness

By forming an etch control material with increased thickness on a first stressed dielectric layer in a dual stress liner approach, the surface topography may be smoothed prior to the deposition of the second stressed dielectric material, thereby allowing the deposition of an increased amount of stressed material while not contributing to yield loss caused by deposition-related defects.