Extended synchronized clock

Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with the first clock signal.

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Bibliographische Detailangaben
Hauptverfasser:	Dour, Navneet, Salmon, Joe H
Format:	Patent
Sprache:	eng
Online-Zugang:	Volltext bestellen
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Beschreibung
Zusammenfassung:	Some embodiments are directed to circuits comprising first and second PLLs. The first PLL generates a first clock signal based on a reference clock signal. The second PLL generates a second clock signal based on the reference clock signal and is synchronized with the first clock signal.