Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains

A device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains is described. In one embodiment, a memory device comprises two or more port synchronization logic devices, a port multiplexing logic, and a single-ported memory core. The port multiplexing logic devices synchronize information communicated between ports associated with the port synchronization logic devices and the single-ported memory core by synchronizing the information between port clocks and a core clock.