Dynamic adaptive read return of DRAM data

Dynamic adaptive read return of DRAM data

An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsiv...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kareenahalli, Suryaprasad, Bogin, Zohar
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:An integrated circuit communicates with memory devices. Data from the memory devices arrives at the integrated circuit with varying propagation delays. The integrated circuit detects the arrival of data from the memory devices, and stores the data in FIFOs. A FIFO drain signal is generated responsive to the detection of the data arrival.