ESD protection circuit and method

dd1 dd2 dd1SSssA system includes a driving device operating at first supply voltage Vand having a CMOS output. A driven devise operates at a second supply voltage Vlower than the first supply voltage V, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first res...

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Bibliographische Detailangaben
Hauptverfasser: Lin, Shu-Huei, Gan, Chong-Gim, Wu, Yi-Hsun, Lin, Yu-Chang
Format: Patent
Sprache:eng
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Zusammenfassung:dd1 dd2 dd1SSssA system includes a driving device operating at first supply voltage Vand having a CMOS output. A driven devise operates at a second supply voltage Vlower than the first supply voltage V, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail V. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to V. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.