Daisy chainable self timed memory chip

A memory chip suitable for use in a daisy chain of memory chips. Timing of an array on the memory chip is dynamically determined by circuitry on the memory chip that tracks an access timing of the array. The memory chip is configured to receive an address/command word, determine if the address/command word is directed to the memory chip. If so, the array on the memory chip is accessed according to the address command word. If the address/command word is not directed to the memory chip, the memory chip re-drives the address/command word from an output of the memory chip.