Clock distribution chip for generating both zero-delay and non-zero-delay clock signals

In one embodiment of the invention, a clock distribution (CD) chip has one or more input pins, input buffer circuitry, clock generation and distribution circuitry, fanout circuitry, one or more output pins, a feedback pin, and feedback buffer circuitry. Based on single-ended or differential input clock signals applied to the input pins, the CD chip can be programmably configured to generate zero, one, or more zero-delay (ZD) output clock signals and zero, one, or more non-zero-delay (NZD) output clock signals for simultaneous presentation at the output pins.