Method and apparatus for manufacturing multiple circuit patterns using a multiple project mask

A method and apparatus are disclosed for fabricating a substrate having a plurality of circuit patterns. The substrate is exposed to a primary mask having a plurality of the desired circuit patterns, surrounded by one or more exclusion regions, and a secondary mask having a pattern corresponding to the exclusion regions that satisfies at least one design rule for a subsequent process. The primary and secondary masks are exposed on the substrate in any order before the resist patterns are developed. The pattern on the secondary mask may comprise, for example, an array of fill patterns. The pattern on the secondary mask may satisfy design rules for more than one process level so that a single secondary mask can be utilized for multiple process levels. In addition, the substrate only needs to be exposed to the secondary mask for process levels where the exclusion regions violate a design rule.