Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations

A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple op...

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Bibliographische Detailangaben
Hauptverfasser: Ahmed, Ashraf, Goveas, Kelvin Domnic, Clark, Michael, Ilic, Jelena
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit mode is indicated, or multiple operations, when the reduced-bit mode is indicated.