Method and apparatus capable of mitigating third order inter-modulation distortion in electronic circuits

Method and apparatus capable of mitigating third order inter-modulation distortion in electronic circuits

An embodiment of the present invention provides a method of mitigating third order inter-modulation distortion in electronic circuits, comprising estimating an IP3 of the circuits using an empirical equation which includes at least one or more of the factors IP3˜IP3o−20 log Q+10 log F+10 log C−17.3...

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Bibliographische Detailangaben
1. Verfasser: Du Toit, Nicolaas
Format: Patent
Sprache:eng
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Zusammenfassung:An embodiment of the present invention provides a method of mitigating third order inter-modulation distortion in electronic circuits, comprising estimating an IP3 of the circuits using an empirical equation which includes at least one or more of the factors IP3˜IP3o−20 log Q+10 log F+10 log C−17.3 log k dBm and optimizing one or more of the factors such that the third order inter-modulation distortion is mitigated.