Test structure and method for detecting and studying crystal lattice dislocation defects in integrated circuit devices

A test structure (′) having an array of test devices for detecting and studying defects that can occur in an integrated circuit device, e.g., a transistor, due to the relative positioning of one component of the device with respect to another component of the device. The test devices in the array are of a like kind, but vary in their configuration. The differences in the configurations are predetermined and selected with the intent of forcing defects to occur within at least some of the test devices. During testing, the responses of the test devices are sensed so as to determine whether or not a defect has occurred in any one or more of the test devices. If a defective test device is detected, the corresponding wafer may be subjected to physical failure analysis for yield learning.