Flip-flop circuit

To keep input capacitance and driving capability at respective data input and output terminals of a flip-flop circuit, the flip-flop includes: a master latch portion; a slave latch portion; and a data output selecting portion. The master latch portion includes a tri-state inverter, which is connected to the input terminal. The data output selecting portion is constituted by two pass gates and an inverter, which is connected to the output terminal. The input capacitance of the flip-flop circuit is determined by gate capacitances of transistors constituting the tri-state inverter connected to the input terminal. The driving capability of the flip-flop circuit is determined by the driving capability of the inverter connected to the output terminal. Accordingly, both the input capacitance and the driving capability are kept constant, irrespective of the state of a timing signal such as a clock signal.