Flash memory device with program current compensation

A memory device includes a flash memory cell array comprising a plurality of flash memory cells, a program voltage generator circuit configured to generate a program voltage at an output thereof and a program circuit coupled to the output of the program voltage generator circuit and configured to couple the output of the program voltage generator circuit to the memory cell array. The memory cell array responsively loads the output of the program voltage generator circuit an amount that varies in correlation with data applied to the memory cell array. The device further includes a program current compensator circuit coupled to the output of the program voltage generator circuit and configured to load the program voltage generator circuit in correlation to the data applied to the memory cell array.