Device having reduced chemical mechanical planarization

The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardened...

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Bibliographische Detailangaben
1. Verfasser: Ramarajan, Suresh
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present technique is directed toward the fabrication of integrated circuits and provides for the production of a hardened metal layer on the surface of a semiconductor wafer to reduce the amount of material removed during chemical mechanical planarization (CMP) of the metal layer. This hardened layer may be produced, for example, by oxidizing the metal surface and/or coating the metal surface with a polymer. In one implementation, a relatively thick and dense oxide layer is formed on the wafer metal surface prior to CMP, by injecting, for example, an oxidant, such as oxygen or ozone, near the end of an annealing cycle. The hardened metal beneficially protects recessed regions from CMP chemical attack and CMP pad deformation, and thus reduces the thickness-to-planarity, dishing, and waste generation realized during CMP.