Parallel input/output self-test circuit and method

Parallel input/output self-test circuit and method

A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (...

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Hauptverfasser: Krishnan, Gopalakrishnan Perur, Vadlamani, Eswar, Munday, Tarjinder Singh
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Sprache:eng
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creator Krishnan, Gopalakrishnan Perur
Vadlamani, Eswar
Munday, Tarjinder Singh
description A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07447958</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07447958</sourcerecordid><originalsourceid>FETCH-uspatents_grants_074479583</originalsourceid><addsrcrecordid>eNrjZDAKSCxKzMlJzVHIzCsoLdHPLy0BUgrFqTlpuiWpxSUKyZlFyaWZJQqJeSkKuaklGfkpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYm5iYW5paGBOhBAC2-C06</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Parallel input/output self-test circuit and method</title><source>USPTO Issued Patents</source><creator>Krishnan, Gopalakrishnan Perur ; Vadlamani, Eswar ; Munday, Tarjinder Singh</creator><creatorcontrib>Krishnan, Gopalakrishnan Perur ; Vadlamani, Eswar ; Munday, Tarjinder Singh ; Cypress Semiconductor Corporation</creatorcontrib><description>A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit.</description><language>eng</language><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7447958$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64038</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7447958$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Krishnan, Gopalakrishnan Perur</creatorcontrib><creatorcontrib>Vadlamani, Eswar</creatorcontrib><creatorcontrib>Munday, Tarjinder Singh</creatorcontrib><creatorcontrib>Cypress Semiconductor Corporation</creatorcontrib><title>Parallel input/output self-test circuit and method</title><description>A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDAKSCxKzMlJzVHIzCsoLdHPLy0BUgrFqTlpuiWpxSUKyZlFyaWZJQqJeSkKuaklGfkpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYm5iYW5paGBOhBAC2-C06</recordid><startdate>20081104</startdate><enddate>20081104</enddate><creator>Krishnan, Gopalakrishnan Perur</creator><creator>Vadlamani, Eswar</creator><creator>Munday, Tarjinder Singh</creator><scope>EFH</scope></search><sort><creationdate>20081104</creationdate><title>Parallel input/output self-test circuit and method</title><author>Krishnan, Gopalakrishnan Perur ; Vadlamani, Eswar ; Munday, Tarjinder Singh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_074479583</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Krishnan, Gopalakrishnan Perur</creatorcontrib><creatorcontrib>Vadlamani, Eswar</creatorcontrib><creatorcontrib>Munday, Tarjinder Singh</creatorcontrib><creatorcontrib>Cypress Semiconductor Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Krishnan, Gopalakrishnan Perur</au><au>Vadlamani, Eswar</au><au>Munday, Tarjinder Singh</au><aucorp>Cypress Semiconductor Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Parallel input/output self-test circuit and method</title><date>2008-11-04</date><risdate>2008</risdate><abstract>A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit.</abstract><oa>free_for_read</oa></addata></record>
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title Parallel input/output self-test circuit and method
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T12%3A31%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Krishnan,%20Gopalakrishnan%20Perur&rft.aucorp=Cypress%20Semiconductor%20Corporation&rft.date=2008-11-04&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07447958%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true