Parallel input/output self-test circuit and method

A parallel data transmission test system can include a receiver section having input selector circuits (-O to -N) that provide a received test data to logic adjust circuits (-O to -N) that "logically align" multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit.