Low latency computation in real time utilizing a DSP processor

A method for applying a computation utilizing a processor capable of accessing an on-chip memory and data from an off-chip source, the method comprising the iterative steps of retrieving at the on-chip memory successive frames of input data from the off-chip source; computing from a current input frame of data available in the on-chip memory current result elements for completing a current output frame of results, and pre-computing from the current frame of input data future result elements for contributing to at least one future output frame of results.