Processor system having accelerator of Java-type of programming language

In a processor system comprising of a processor having an instruction decoder , a general register composed of a plurality of register areas and at least one ALU , and a Java accelerator for converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java accelerator is composed of a bytecode translator for converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unit for mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit , the supply of the native instruction from the bytecode translator to the instruction decoder is inhibited.