Selective silicon deposition for planarized dual surface orientation integration

A semiconductor process and apparatus provide a planarized hybrid substrate having a more uniform polish surface by thickening an SOI semiconductor layer in relation to a previously or subsequently formed epitaxial silicon layer with a selective silicon deposition process that covers the SOI semiconductor layer with a crystalline semiconductor layer. By forming first gate electrodes over a first SOI substrate using deposited (100) silicon and forming second gate electrodes over an epitaxially grown (110) silicon substrate, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.