Multiplexer cell and multiplexer circuit arrangement and coding device for use in a multiplexer circuit arrangement of this kind

01DE0D01DE0110A multiplexer cell for converting an input signal (D, D) with a data input rate (f) into an output signal (E) with a data output rate (f), which in particular is twice the size of the data input rate, is proposed. For this purpose the multiplexer cell according to the invention has a clock input connection for supplying a clock signal (C), the frequency of which is the same as the data input rate (f), a first and a second data input connection for supplying a first or second input signal (D, D) at the data input rate (f), a data output connection for the output of the output signal (E) at the data output rate (f), a first and a second master-slave register circuit, the inputs of which are connected to the first or second data input connection and the clock inputs of which are connected to the clock input connection, for the flank controlled output of the first or second input signal (D, D), a delay circuit the input of which is connected to the output of the second master-slave register circuit and the clock input of which is connected to the clock input connection, for the delayed output of the second input signal (D), wherein the delay is half a clock period of the clock signal (C) and an XOR gate circuit, the first input of which is connected to the output of the first master-slave register circuit, the second input of which is connected to the output of the delay circuit and the output of which is connected to the data output connection.