Transaction flow control mechanism for a bus bridge

A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.