Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor

A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same "front-end" pipelines within an Instruction Unit. Within the shared pipelines the Instruction Unit checks the GP instructions for dependencies and resolves these dependencies. At the dispatch point within the pipelines the Instruction Unit sends valid GP instructions to the GP Unit and SIMD instructions to an SIMD issue queue. In the SIMD issue queue the Instruction Unit checks the SIMD instructions for dependencies and resolves these dependencies. Then the SIMD issue queue dispatches the SIMD instructions to the SIMD Unit. Accordingly, dependencies involving SIMD instructions do not affect GP instructions because the SIMD dependencies are checked and resolved independently.