High speed non-volatile electronic memory configuration

A high speed non-volatile electronic memory configuration and method is disclosed. In one particular exemplary embodiment, the high speed non-volatile electronic memory configuration may be realized comprising a high speed volatile memory, a non-volatile memory coupled to the high speed volatile memory, a controller coupled to the high speed volatile memory and the non-volatile memory, and a power level detector that detects when power is above a particular minimum operating voltage level. The controller monitors data storage changes made within the high speed volatile memory and controls the transfer of stored data from the high speed volatile memory to the non-volatile memory, and vice-versa, when power is above the particular minimum operating voltage level.