Internal signal test device and method thereof

An internal signal test device tests a cycle of a specific internal signal by distinguishing a high level period and a low level period of the internal signal, at a wafer and package state by using an external test equipment. The internal signal test device comprises a refresh cycle generating unit, an input/output selecting control unit and an output buffer. The refresh cycle generating unit generates a refresh cycle signal having a predetermined cycle at entry of a refresh mode. The input/output selecting control unit selectively outputs the refresh cycle signal and a data signal in response to a test mode signal. The output control unit outputs an output signal from the input/output selecting control unit to an external output pin in response to an output clock signal controlled by the test mode signal.