Method of inspecting integrated circuits during fabrication

A method and system for inspecting integrated circuit chips during fabrication. The method including: selecting an integrated circuit chip at a selected level of fabrication; determining coordinates of potential failures of the integrated circuit chip based on one or more risk of failure analyses performed ancillary to fabrication of the integrated circuit chip; automatically generating one or more enhanced defect inspection regions for inspecting the integrated circuit chip based on the coordinates; automatically selecting one or more enhanced defect inspection parameters for each of the one or more enhanced defect inspection regions based on the one or more risk of failure analyses; and generating an enhanced defect inspection recipe, the enhanced defect inspection recipe including a location on the integrated circuit chip, an enhanced defect inspection parameter and a value for the enhanced defect inspection parameter for each of the one or more enhanced defect inspection regions.