Method and circuit to implement digital delay lines

A delay line circuit and method to delay digital data in a main memory is provided. The delay line circuit may comprise primary delay line cache, secondary delay line cache, and a cache controller to control communication of data between the secondary delay cache and the primary delay cache. The primary delay line cache may receive digital data to be delayed from a signal processor module, and secondary delay line cache may be connected to the primary delay line cache and the main memory to send data to and receive delayed data from the main memory. Data in the secondary delay line cache may be updated with data from the main memory or with data from the primary delay line cache. The invention extends to a machine-readable medium comprising a set of instructions for executing any of the methods described herein.