Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit

A pattern of voids in an integrated circuit having a first layer, a first layer surface and adjacent lands on the first layer surface, the adjacent lands enclosing spaces and including a second layer of a first isolation material and a third layer of a second isolation material arranged on the second layer. The pattern of voids has a fourth layer of a third isolation material which closes off at least some of the spaces and cannot be deposited on the first isolation material. The fourth layer is arranged on the third layer and has a second layer surface. Spaces that are not closed off by means of the fourth layer are filled with electrically conductive material. In the method for producing a pattern of voids in an integrated circuit, a second layer of a first isolation material is applied to a first layer surface of a first layer. A third layer of a second isolation material is applied to the second layer, the third layer acquiring a second layer surface which is arranged parallel to the first layer surface. Adjacent lands with spaces are formed from the second layer and the third layer. A third isolation material is selectively applied on the adjacent lands to the third layer, such that a fourth layer is formed between and above the adjacent lands. Parallel to the first layer surface, the fourth layer is partially removed until the second layer surface is uncovered. The fourth layer is completely removed above some spaces, and finally these spaces are filled with electrically conductive material in order to form electrical contacts between the first layer surface and the second layer surface, resulting in a pattern of voids.