Integrated circuit, its fabrication process and memory cell incorporating such a circuit

This integrated circuit comprises a capacitor formed above a substrate inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure for connection to the capacitor.The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.