Processing system and memory module having frequency selective memory

A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.