Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology

A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.

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Hauptverfasser:	Chang, Kuan-Lun, Liu, Ruey-Hsin, Liou, Tsyr-Shyang, Chiang, Chih-Min, Tsai, Jun-Lin
Format:	Patent
Sprache:	eng
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creator	Chang, Kuan-Lun Liu, Ruey-Hsin Liou, Tsyr-Shyang Chiang, Chih-Min Tsai, Jun-Lin
description	A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.
format	Patent
fullrecord	<record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07250344</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07250344</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072503443</originalsourceid><addsrcrecordid>eNrjZIjxTS3JyE9RyE9TSMsvys3MS1dIVCjOSMzJyS9XKClKzUvO0E1JTS2AshUyi_NzEksy8_MUilLTQRRQF1CHU6azr3-wPohQKElNzsjLz8lPr-RhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzI1MDYxMSYCCUA0007cQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology</title><source>USPTO Issued Patents</source><creator>Chang, Kuan-Lun ; Liu, Ruey-Hsin ; Liou, Tsyr-Shyang ; Chiang, Chih-Min ; Tsai, Jun-Lin</creator><creatorcontrib>Chang, Kuan-Lun ; Liu, Ruey-Hsin ; Liou, Tsyr-Shyang ; Chiang, Chih-Min ; Tsai, Jun-Lin ; Taiwan Semiconductor Manufacturing Company, Ltd</creatorcontrib><description>A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7250344$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7250344$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chang, Kuan-Lun</creatorcontrib><creatorcontrib>Liu, Ruey-Hsin</creatorcontrib><creatorcontrib>Liou, Tsyr-Shyang</creatorcontrib><creatorcontrib>Chiang, Chih-Min</creatorcontrib><creatorcontrib>Tsai, Jun-Lin</creatorcontrib><creatorcontrib>Taiwan Semiconductor Manufacturing Company, Ltd</creatorcontrib><title>Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology</title><description>A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZIjxTS3JyE9RyE9TSMsvys3MS1dIVCjOSMzJyS9XKClKzUvO0E1JTS2AshUyi_NzEksy8_MUilLTQRRQF1CHU6azr3-wPohQKElNzsjLz8lPr-RhYE1LzClO5YXS3AwKbq4hzh66pcUFiSWpeSXF8elFiSDKwNzI1MDYxMSYCCUA0007cQ</recordid><startdate>20070731</startdate><enddate>20070731</enddate><creator>Chang, Kuan-Lun</creator><creator>Liu, Ruey-Hsin</creator><creator>Liou, Tsyr-Shyang</creator><creator>Chiang, Chih-Min</creator><creator>Tsai, Jun-Lin</creator><scope>EFH</scope></search><sort><creationdate>20070731</creationdate><title>Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology</title><author>Chang, Kuan-Lun ; Liu, Ruey-Hsin ; Liou, Tsyr-Shyang ; Chiang, Chih-Min ; Tsai, Jun-Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072503443</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Chang, Kuan-Lun</creatorcontrib><creatorcontrib>Liu, Ruey-Hsin</creatorcontrib><creatorcontrib>Liou, Tsyr-Shyang</creatorcontrib><creatorcontrib>Chiang, Chih-Min</creatorcontrib><creatorcontrib>Tsai, Jun-Lin</creatorcontrib><creatorcontrib>Taiwan Semiconductor Manufacturing Company, Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chang, Kuan-Lun</au><au>Liu, Ruey-Hsin</au><au>Liou, Tsyr-Shyang</au><au>Chiang, Chih-Min</au><au>Tsai, Jun-Lin</au><aucorp>Taiwan Semiconductor Manufacturing Company, Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology</title><date>2007-07-31</date><risdate>2007</risdate><abstract>A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.</abstract><oa>free_for_read</oa></addata></record>
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title	Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T15%3A38%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chang,%20Kuan-Lun&rft.aucorp=Taiwan%20Semiconductor%20Manufacturing%20Company,%20Ltd&rft.date=2007-07-31&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07250344%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true