Arrangements having IC voltage and thermal resistance designated on a per IC basis

Arrangements having IC voltage and thermal resistance designated on a per IC basis

Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testin...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Arabi, Tawfik, Ma, Hung-Piao, Iovino, Gregory M, Rotem, Shai, Kornfeld, Avner, Taylor, Gregory F
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Arabi, Tawfik
Ma, Hung-Piao
Iovino, Gregory M
Rotem, Shai
Kornfeld, Avner
Taylor, Gregory F
description Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07233162</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07233162</sourcerecordid><originalsourceid>FETCH-uspatents_grants_072331623</originalsourceid><addsrcrecordid>eNqNjTEKwkAQRbexEPUO_wKCZkFrCYppg72M7rgJbCZhd8z5HcEDWL1fvMdfuvaUM0nkgUULOpp7iWhqzGNSigySAO04D5SQufRFSZ6MYDMKKQeMAsLE-Vs9yIy1W7woFd78uHK4nG_1dfsukxX2c4_2adgdK-_3h8r_oXwAesk4BQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Arrangements having IC voltage and thermal resistance designated on a per IC basis</title><source>USPTO Issued Patents</source><creator>Arabi, Tawfik ; Ma, Hung-Piao ; Iovino, Gregory M ; Rotem, Shai ; Kornfeld, Avner ; Taylor, Gregory F</creator><creatorcontrib>Arabi, Tawfik ; Ma, Hung-Piao ; Iovino, Gregory M ; Rotem, Shai ; Kornfeld, Avner ; Taylor, Gregory F ; Intel Corporation</creatorcontrib><description>Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.</description><language>eng</language><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7233162$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,776,798,881,64012</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7233162$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Arabi, Tawfik</creatorcontrib><creatorcontrib>Ma, Hung-Piao</creatorcontrib><creatorcontrib>Iovino, Gregory M</creatorcontrib><creatorcontrib>Rotem, Shai</creatorcontrib><creatorcontrib>Kornfeld, Avner</creatorcontrib><creatorcontrib>Taylor, Gregory F</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><title>Arrangements having IC voltage and thermal resistance designated on a per IC basis</title><description>Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNqNjTEKwkAQRbexEPUO_wKCZkFrCYppg72M7rgJbCZhd8z5HcEDWL1fvMdfuvaUM0nkgUULOpp7iWhqzGNSigySAO04D5SQufRFSZ6MYDMKKQeMAsLE-Vs9yIy1W7woFd78uHK4nG_1dfsukxX2c4_2adgdK-_3h8r_oXwAesk4BQ</recordid><startdate>20070619</startdate><enddate>20070619</enddate><creator>Arabi, Tawfik</creator><creator>Ma, Hung-Piao</creator><creator>Iovino, Gregory M</creator><creator>Rotem, Shai</creator><creator>Kornfeld, Avner</creator><creator>Taylor, Gregory F</creator><scope>EFH</scope></search><sort><creationdate>20070619</creationdate><title>Arrangements having IC voltage and thermal resistance designated on a per IC basis</title><author>Arabi, Tawfik ; Ma, Hung-Piao ; Iovino, Gregory M ; Rotem, Shai ; Kornfeld, Avner ; Taylor, Gregory F</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_072331623</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Arabi, Tawfik</creatorcontrib><creatorcontrib>Ma, Hung-Piao</creatorcontrib><creatorcontrib>Iovino, Gregory M</creatorcontrib><creatorcontrib>Rotem, Shai</creatorcontrib><creatorcontrib>Kornfeld, Avner</creatorcontrib><creatorcontrib>Taylor, Gregory F</creatorcontrib><creatorcontrib>Intel Corporation</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Arabi, Tawfik</au><au>Ma, Hung-Piao</au><au>Iovino, Gregory M</au><au>Rotem, Shai</au><au>Kornfeld, Avner</au><au>Taylor, Gregory F</au><aucorp>Intel Corporation</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Arrangements having IC voltage and thermal resistance designated on a per IC basis</title><date>2007-06-19</date><risdate>2007</risdate><abstract>Systems for testing a plurality of integrated circuits at a plurality of frequencies and voltages is disclosed. In one embodiment, a plurality of integrated circuits is tested at least once within a predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the predetermined set, the integrated circuit is retested at a different predetermined set of combinations of frequencies and voltages. If the integrated circuit fails testing within any combination of a frequency and voltage within the different predetermined set, the integrated circuit is discarded.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_07233162
source USPTO Issued Patents
title Arrangements having IC voltage and thermal resistance designated on a per IC basis
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-05T14%3A06%3A28IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Arabi,%20Tawfik&rft.aucorp=Intel%20Corporation&rft.date=2007-06-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07233162%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true