FIFO-register and digital signal processor comprising a FIFO-register

iA FIFO-register according to the invention comprises a sequence of register cells (.m), which register cells have a data section and a status section. Data (Din) provided at an input is shifted via the data sections in the register cells to an output. The status section of each cell indicates whether the data section of that cell contains valid data. The status section of a cell comprises a control unit coupled to a status input, to a status output and to a clock input, and generates an output clock signal (Cl), which controls charge controlling elements coupled to the status input and the status output and controls the data section. The status output of a status section and the status input (′) of its successor (′) share a common capacitive node.