Method and apparatus for clock division on a programmable logic device

According to one example embodiment, a complex, programmable logic device (CPLD-type) has logic blocks and Input/Output (I/O) pads interconnected via a programmable interconnect array. A dedicated logic block is directly coupled to I/O pads, which provides external access to the dedicated logic block without traversing the programmable interconnect array. The dedicated logic block may include a clock divider module for providing a divided clock to the CPLD.