Memory controller for synchronous burst transfers

A processing system includes a processor, a memory controller, and a memory subsystem. The memory controller includes a processor interface, a memory data interface, sequential transfer circuitry, and transaction processing logic. Randomly accessed data units of a first size are synchronously exchanged between the memory data interface of the memory controller and the memory subsystem via a transfer sequence comprising a predetermined plurality of sequential transfers of data units of a size smaller than the first size.