Clock frequency detect with programmable jitter tolerance

An apparatus and method is disclosed for programmable determination of frequency, phase, and jitter relationship of a first clock and a second clock in an electronic system. In a first, initialization, mode, a first register and a second register are initialized with a first bit pattern and a second bit pattern, respectively. In a second, normal, mode, the first clock is coupled to the first register and the second clock is coupled to the second register. A compare unit observes the bit patterns of the first and second registers and reports when one or more predetermined relationships between the first clock and the second clock occur.