Apparatus and method for initiating a sleep state in a system on a chip device

An apparatus and method is disclosed for initiating a sleep state in a system-on-a-chip (SOC) device. The apparatus comprises a bus controller coupled to a central processing unit (CPU) and a power management controller that is coupled to the bus controller and to a plurality of SOC modules. The power management controller sends control signals to the bus controller and to the SOC modules to coordinate the shutting down of power to the SOC modules during a process in which the power management controller places the SOC modules of the system-on-a-chip (SOC) device into a sleep state.