Stabilization method for drain voltage in non-volatile multi-level memory cells and related memory device
A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a common circuit node by a metal line co...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a common circuit node by a metal line conduction path having a parasitic intrinsic resistance. A feedback path is advantageously provided between the common circuit node and an input of the regulator. |
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