Data transmission/reception system

In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system, whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system, whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system, the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system is realized.