Integrated circuit and method of manufacturing an integrated circuit and package

Integrated circuit and method of manufacturing an integrated circuit and package

A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadsid...

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Hauptverfasser: Devnani, Nurwati S, Barnes, James Oliver, Moore, Charles E, Lai, Benny W H
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Sprache:eng
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creator Devnani, Nurwati S
Barnes, James Oliver
Moore, Charles E
Lai, Benny W H
description A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.
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fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_07001834</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>07001834</sourcerecordid><originalsourceid>FETCH-uspatents_grants_070018343</originalsourceid><addsrcrecordid>eNrjZAjwzCtJTS9KLElNUUjOLEouzSxRSMxLUchNLcnIT1HIT1PITcwrTUtMLiktysxLB8opZGLXUZCYnJ2YnsrDwJqWmFOcyguluRkU3FxDnD10S4sLgHrySorjgZpBlIG5gYGhhbGJMRFKAF8aODI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit and method of manufacturing an integrated circuit and package</title><source>USPTO Issued Patents</source><creator>Devnani, Nurwati S ; Barnes, James Oliver ; Moore, Charles E ; Lai, Benny W H</creator><creatorcontrib>Devnani, Nurwati S ; Barnes, James Oliver ; Moore, Charles E ; Lai, Benny W H ; Agilent Technologies, Inc</creatorcontrib><description>A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.</description><language>eng</language><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7001834$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,780,802,885,64038</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/7001834$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Devnani, Nurwati S</creatorcontrib><creatorcontrib>Barnes, James Oliver</creatorcontrib><creatorcontrib>Moore, Charles E</creatorcontrib><creatorcontrib>Lai, Benny W H</creatorcontrib><creatorcontrib>Agilent Technologies, Inc</creatorcontrib><title>Integrated circuit and method of manufacturing an integrated circuit and package</title><description>A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZAjwzCtJTS9KLElNUUjOLEouzSxRSMxLUchNLcnIT1HIT1PITcwrTUtMLiktysxLB8opZGLXUZCYnJ2YnsrDwJqWmFOcyguluRkU3FxDnD10S4sLgHrySorjgZpBlIG5gYGhhbGJMRFKAF8aODI</recordid><startdate>20060221</startdate><enddate>20060221</enddate><creator>Devnani, Nurwati S</creator><creator>Barnes, James Oliver</creator><creator>Moore, Charles E</creator><creator>Lai, Benny W H</creator><scope>EFH</scope></search><sort><creationdate>20060221</creationdate><title>Integrated circuit and method of manufacturing an integrated circuit and package</title><author>Devnani, Nurwati S ; Barnes, James Oliver ; Moore, Charles E ; Lai, Benny W H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_070018343</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Devnani, Nurwati S</creatorcontrib><creatorcontrib>Barnes, James Oliver</creatorcontrib><creatorcontrib>Moore, Charles E</creatorcontrib><creatorcontrib>Lai, Benny W H</creatorcontrib><creatorcontrib>Agilent Technologies, Inc</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Devnani, Nurwati S</au><au>Barnes, James Oliver</au><au>Moore, Charles E</au><au>Lai, Benny W H</au><aucorp>Agilent Technologies, Inc</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit and method of manufacturing an integrated circuit and package</title><date>2006-02-21</date><risdate>2006</risdate><abstract>A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.</abstract><oa>free_for_read</oa></addata></record>
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title Integrated circuit and method of manufacturing an integrated circuit and package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T19%3A21%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Devnani,%20Nurwati%20S&rft.aucorp=Agilent%20Technologies,%20Inc&rft.date=2006-02-21&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E07001834%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true