System and method for synchronizing divide-by counters

ABABABABABABABA synchronization system capable of simultaneously resetting frequency divide-by counters of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit for each processor that simulates in the undivided signal (Mclk/1 signal) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal. A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal and sends an asynchronous offset signal to a counter re-setter that resets the divide-by counter to zero based on the offset signal.