Method and apparatus for no-latency conditional branching

An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction is a binary word specifying a branch condition address and a conditional instruction. The branch unit...

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Bibliographische Detailangaben
Hauptverfasser: Krech, Jr, Alan S, Jordan, Stephen D
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction is a binary word specifying a branch condition address and a conditional instruction. The branch unit has a programmable flag selection memory and a plurality of first flag selectors and determines in hardware whether to branch according to the conditional instruction. Each first flag selector accepts a plurality of available flags and selects a flag based upon contents in the flag selection memory. A second flag selector accepts the flags from the first flag selectors and selects one of the flags to present as a branch flag based upon the branch condition address. The branch flag indicates whether to branch to the destination address.