Chip card circuit with monitored access to a test mode
A circuit for monitoring an entry into a test mode of a chip circuit has a fusible link which can be fired via a firing transistor. A flipflop, which permits access to the test mode, is set by a resulting voltage drop, with the aid of an edge detector. The number of times the test mode has been acce...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A circuit for monitoring an entry into a test mode of a chip circuit has a fusible link which can be fired via a firing transistor. A flipflop, which permits access to the test mode, is set by a resulting voltage drop, with the aid of an edge detector. The number of times the test mode has been accessed can be detected from the number of fired fusible links. |
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