Self aligned vias in dual damascene interconnect, buried mask approach

Methods are disclosed for forming vias, trenches, and interconnects through diffusion barrier, etch-stop, and dielectric materials for interconnection of electrical devices in dual damascene structures of a semiconductor device. A buried via mask at the etch-stop level provides openings with two or more adjacent via misalignment error regions merged into rectangular windows aligned orthogonal to a long axis of the underlying conductive features of a first metal level. The rectangular windows used together with openings in a hard mask form via portions, and the openings in the hard mask provide trench portions. Via and trench portions coincide during trench or via etch, as well as during hard mask or etch-stop layer etch together forming an interconnect cavity, which may then be filled with a conductive material to provide a conductive interconnect between the conductive feature of the first metal level and a second metal level.