Gated diode overvoltage protection

Disclosed herein is a gated diode overvoltage protection circuit. In one embodiment, the circuit includes: a terminal, a gated diode, and a bias circuit. The terminal is configured to convey a voltage signal. The gated diode has an anode, a cathode, and a gate. The gated diode is coupled between the terminal and a predetermined voltage node so as to enter a forward conduction mode during electrostatic discharge (ESD) events, overvoltage conditions, or transient signal excursions. The bias circuit is configured to establish a low-resistance path between the cathode and gate when the gated diode is in a forward conduction mode, and to eliminate the low-resistance path when the gated diode is not in the forward conduction mode.