Semiconductor device and process for producing the same

Semiconductor device and process for producing the same

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Ishitsuka, Norio, Miura, Hideo, Ikeda, Shuji, Suzuki, Norio, Matsuda, Yasushi, Yoshida, Yasuko, Yamamoto, Hirohiko, Kobayashi, Masamichi, Takamatsu, Akira, Shimizu, Hirofumi, Fukuda, Kazushi, Horibe, Shinichi, Nozoe, Toshio
Format: Patent
Sprache:eng
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Ishitsuka, Norio
Miura, Hideo
Ikeda, Shuji
Suzuki, Norio
Matsuda, Yasushi
Yoshida, Yasuko
Yamamoto, Hirohiko
Kobayashi, Masamichi
Takamatsu, Akira
Shimizu, Hirofumi
Fukuda, Kazushi
Horibe, Shinichi
Nozoe, Toshio
description A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
format Patent
fullrecord <record><control><sourceid>uspatents_EFH</sourceid><recordid>TN_cdi_uspatents_grants_06881646</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>06881646</sourcerecordid><originalsourceid>FETCH-uspatents_grants_068816463</originalsourceid><addsrcrecordid>eNrjZDAPTs3NTM7PSylNLskvUkhJLctMTlVIzEtRKCjKT04tLlZIAwoD2UAFmXnpCiUZqQrFibmpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYWVgYmpmYGROhBAC05C70</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and process for producing the same</title><source>USPTO Issued Patents</source><creator>Ishitsuka, Norio ; Miura, Hideo ; Ikeda, Shuji ; Suzuki, Norio ; Matsuda, Yasushi ; Yoshida, Yasuko ; Yamamoto, Hirohiko ; Kobayashi, Masamichi ; Takamatsu, Akira ; Shimizu, Hirofumi ; Fukuda, Kazushi ; Horibe, Shinichi ; Nozoe, Toshio</creator><creatorcontrib>Ishitsuka, Norio ; Miura, Hideo ; Ikeda, Shuji ; Suzuki, Norio ; Matsuda, Yasushi ; Yoshida, Yasuko ; Yamamoto, Hirohiko ; Kobayashi, Masamichi ; Takamatsu, Akira ; Shimizu, Hirofumi ; Fukuda, Kazushi ; Horibe, Shinichi ; Nozoe, Toshio ; Renesas Technology Corp ; Hitachi ULSI Systems Co., Ltd</creatorcontrib><description>A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.</description><language>eng</language><creationdate>2005</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6881646$$EPDF$$P50$$Guspatents$$Hfree_for_read</linktopdf><link.rule.ids>230,308,777,799,882,64018</link.rule.ids><linktorsrc>$$Uhttps://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/6881646$$EView_record_in_USPTO$$FView_record_in_$$GUSPTO$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ishitsuka, Norio</creatorcontrib><creatorcontrib>Miura, Hideo</creatorcontrib><creatorcontrib>Ikeda, Shuji</creatorcontrib><creatorcontrib>Suzuki, Norio</creatorcontrib><creatorcontrib>Matsuda, Yasushi</creatorcontrib><creatorcontrib>Yoshida, Yasuko</creatorcontrib><creatorcontrib>Yamamoto, Hirohiko</creatorcontrib><creatorcontrib>Kobayashi, Masamichi</creatorcontrib><creatorcontrib>Takamatsu, Akira</creatorcontrib><creatorcontrib>Shimizu, Hirofumi</creatorcontrib><creatorcontrib>Fukuda, Kazushi</creatorcontrib><creatorcontrib>Horibe, Shinichi</creatorcontrib><creatorcontrib>Nozoe, Toshio</creatorcontrib><creatorcontrib>Renesas Technology Corp</creatorcontrib><creatorcontrib>Hitachi ULSI Systems Co., Ltd</creatorcontrib><title>Semiconductor device and process for producing the same</title><description>A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2005</creationdate><recordtype>patent</recordtype><sourceid>EFH</sourceid><recordid>eNrjZDAPTs3NTM7PSylNLskvUkhJLctMTlVIzEtRKCjKT04tLlZIAwoD2UAFmXnpCiUZqQrFibmpPAysaYk5xam8UJqbQcHNNcTZQ7e0uCCxJDWvpDg-vSgRRBmYWVgYmpmYGROhBAC05C70</recordid><startdate>20050419</startdate><enddate>20050419</enddate><creator>Ishitsuka, Norio</creator><creator>Miura, Hideo</creator><creator>Ikeda, Shuji</creator><creator>Suzuki, Norio</creator><creator>Matsuda, Yasushi</creator><creator>Yoshida, Yasuko</creator><creator>Yamamoto, Hirohiko</creator><creator>Kobayashi, Masamichi</creator><creator>Takamatsu, Akira</creator><creator>Shimizu, Hirofumi</creator><creator>Fukuda, Kazushi</creator><creator>Horibe, Shinichi</creator><creator>Nozoe, Toshio</creator><scope>EFH</scope></search><sort><creationdate>20050419</creationdate><title>Semiconductor device and process for producing the same</title><author>Ishitsuka, Norio ; Miura, Hideo ; Ikeda, Shuji ; Suzuki, Norio ; Matsuda, Yasushi ; Yoshida, Yasuko ; Yamamoto, Hirohiko ; Kobayashi, Masamichi ; Takamatsu, Akira ; Shimizu, Hirofumi ; Fukuda, Kazushi ; Horibe, Shinichi ; Nozoe, Toshio</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-uspatents_grants_068816463</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2005</creationdate><toplevel>online_resources</toplevel><creatorcontrib>Ishitsuka, Norio</creatorcontrib><creatorcontrib>Miura, Hideo</creatorcontrib><creatorcontrib>Ikeda, Shuji</creatorcontrib><creatorcontrib>Suzuki, Norio</creatorcontrib><creatorcontrib>Matsuda, Yasushi</creatorcontrib><creatorcontrib>Yoshida, Yasuko</creatorcontrib><creatorcontrib>Yamamoto, Hirohiko</creatorcontrib><creatorcontrib>Kobayashi, Masamichi</creatorcontrib><creatorcontrib>Takamatsu, Akira</creatorcontrib><creatorcontrib>Shimizu, Hirofumi</creatorcontrib><creatorcontrib>Fukuda, Kazushi</creatorcontrib><creatorcontrib>Horibe, Shinichi</creatorcontrib><creatorcontrib>Nozoe, Toshio</creatorcontrib><creatorcontrib>Renesas Technology Corp</creatorcontrib><creatorcontrib>Hitachi ULSI Systems Co., Ltd</creatorcontrib><collection>USPTO Issued Patents</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ishitsuka, Norio</au><au>Miura, Hideo</au><au>Ikeda, Shuji</au><au>Suzuki, Norio</au><au>Matsuda, Yasushi</au><au>Yoshida, Yasuko</au><au>Yamamoto, Hirohiko</au><au>Kobayashi, Masamichi</au><au>Takamatsu, Akira</au><au>Shimizu, Hirofumi</au><au>Fukuda, Kazushi</au><au>Horibe, Shinichi</au><au>Nozoe, Toshio</au><aucorp>Renesas Technology Corp</aucorp><aucorp>Hitachi ULSI Systems Co., Ltd</aucorp><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and process for producing the same</title><date>2005-04-19</date><risdate>2005</risdate><abstract>A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_uspatents_grants_06881646
source USPTO Issued Patents
title Semiconductor device and process for producing the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T03%3A35%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-uspatents_EFH&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ishitsuka,%20Norio&rft.aucorp=Renesas%20Technology%20Corp&rft.date=2005-04-19&rft_id=info:doi/&rft_dat=%3Cuspatents_EFH%3E06881646%3C/uspatents_EFH%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true